Advanced Vertical Nanostructure Integration: Streamlined Planarisation for Electrical Contacting

TO-123 • PT 1.2726 • As of 10/2023
Peter Grünberg Institute
Semiconductor Nanoelectronics (PGI-9)

Technology

Self-organized nanostructures, particularly semiconductor nanowires, have been extensively researched and could soon be used as fundamental building blocks in computer chips. These nanowires offer superior electron mobility compared to traditional silicon CMOS technology, making them attractive for various applications, including optoelectronics, spintronics, and quantum computing. However, integrating nanowires in spintronics poses challenges due to the need for electrical contact with magnetizable electrodes, which requires prior planarization of the nanostructures.

Problem addressed

Integrating nanowires in spintronics poses challenges due to the need for electrical contact with magnetizable electrodes, which requires prior planarization of the nanostructures. Previous methods, such as using thin metal layers for electrical contact, suffer from geometry-related interruptions and unwanted magnetic domain formation, rendering the devices unusable for spintronics applications. Additionally, the vertical integration of horizontally aligned nanowires faces significant process-related difficulties, as chemical mechanical planarization (CMP) cannot be applied to nanowires without compromising their structural integrity.

Solution

Our invention presents a method for planarizing nanostructures, specifically nanowires, which offers significant advancements in electrical contact and vertical integration of these structures. By utilizing a removable lacquer layer on a transfer substrate, we enable the creation of a planar surface for efficient electrical contact with materials like titanium/gold or ferromagnets.

Additionally, our method allows for aligning nanostructures of varying sizes on a single plane, enhancing versatility. The ability to vertically stack these structures is a key aspect of our invention, providing new possibilities for simplified integration.

Benefits and Potential Use

The applications of our technology extend to various fields, including spintronics, traditional micro- and nanoelectronics, and nanowire-based logic. In computer chip processing, our method facilitates the vertical integration of semiconductor nanostructures, while in spintronics, it enables the production of nanowire components. Moreover, our scalable and transferable process allows for the deposition of ultra-thin dielectrics on nanostructures, enhancing the control of field-effect transistors.

The selective conversion of lacquer through electron beam lithography also creates freestanding nanostructures, beneficial for gas sensors and water splitting applications. Furthermore, our method opens avenues for chemical sensors, micro- and nanofluidic channels, DNA analysis, and nanophotonics, leveraging the ordered nanostructures at the interface of transparent oxide matrices.

Development Status and Next Steps

Forschungszentrum Jülich has extensive expertise in this field and holds several patents. The technology described above has already been initially verified through prototypes and is continuously being developed further. The Peter Grünberg Institute (PGI-9) – Semiconductor Nanoelectronics – already cooperates with numerous national and international companies and scientific partners. Forschungszentrum Jülich focuses on energy and cost-efficient devices, suitable for various emerging technologies. We are continuously seeking for cooperation partners and/or licensees in this and adjacent areas of research and applications.

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