Advanced Non-Volatile Memory Technology with Stable Multi-State Storage Capability

TO-119 • PT 1.2617 • As of 10/2023
Peter Grünberg Institute
Electronic Materials (PGI-7)

Technology

Our invention presents a method for reading a non-volatile memory element having two stable states. The memory element comprises a between the two states, the current state can be determined. The invention introduces a fixed capacitance connected in series with the memory cell to improve the signal strength during capacitive reading. We have found that the second memory cell is not required for capacitive reading. In addition, our invention explores memory devices that combine a field-effect transistor or DRAM structure with a resistive memory cell or an antiserial series connection of such memory cells.

Problem addressed

Passive resistive memory cells have been a simple and compact alternative to charge-based memories like flash memories. However, in large arrays of these cells, parasitic current paths through inactive cells limit the maximum achievable array size. Previous solutions involved forming anti-serial connections of two memory cells, where each cell acted as a high-resistance path in parasitic currents. This allowed for larger arrays but required destructive readout and complex manufacturing processes. Another approach involved using differently fabricated cells in series, enabling non-destructive readout but sacrificing symmetry and increasing technological complexity. The present invention addresses these limitations.

Solution

Our innovative technology offers several advantages. Firstly, it provides a more cost-effective and compact solution for storing information, as the fixed capacitance is easier to implement than a second memory cell.

Additionally, the use of capacitive reading eliminates the need for a high-impedance resistance, resulting in lower power consumption and improved stability. The fixed capacitance and memory cell capacitance ensure optimal signal quality. Furthermore, the configuration allows for greater flexibility in circuit optimisation, such as increasing the switching voltage. This technology is particularly suitable for valence-change-based resistive memories using CMOS-compatible materials.

Benefits and Potential Use

Our technology offers versatile and efficient non-volatile memory solutions. It can be integrated into existing memory technologies such as MOSFETs, flash memories or EEPROMs without significant modifications. The fixed capacitance of the memory cell, which serves as the gate dielectric of a field-effect transistor, enables efficient control and sensitive readout of the memory cell. The thin design of the gate dielectric reduces space requirements without compromising volatility. Alternatively, our technology can be combined with DRAM cells by connecting either a resistive memory cell or an antiserial array of resistive memory cells in series with the DRAM capacitor. This configuration allows capacitive readout and can be easily integrated into the existing DRAM structure. The resistive memory cell can be fabricated as a planar metal-insulator-metal structure, ensuring compatibility with current manufacturing processes.

Development Status and Next Steps

Forschungszentrum Jülich has extensive expertise in this field and holds several patents. The technology described above has already been initially verified through prototypes and is continuously being developed further. The Peter Grünberg Institute (PGI-7) – Electronic Materials – already cooperates with numerous national and international companies and scientific partners. Forschungszentrum Jülich focuses on energy and cost-efficient devices, suitable for various emerging technologies. We are continuously seeking for cooperation partners and/or licensees in this and adjacent areas of research and applications.

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